Bonded my first IC!

[Cliff Schecht]

I learned how to use a bonding machine tonight and bonded my first IC design to a board to start testing. Since we get the dies in unpackaged, we have to adhere the handle (back-side of the IC, aka the substrate) to a big gold pad and break out all of the IC pads to the board pads.

As much as I was warned that the bonding machine was a bear to use, it wasn't that hard all things considered. The gold bond wires are thinner than hair though so it's not super easy to rethread the needle if you break the wire or have a misfire.

Anybody else used a bonding machine?

The design is an envelope tracking power supply that, as the name implies, varies the output voltage based on the input signal. This is meant to go onto RF PA's to vary the drain voltage with the input signal such that the PA is always operating in the more efficient saturated region. Definitely not a new idea but the power levels I'm working with have not been integrated on-chip yet. If I accomplish this then I might have a chance at publishing in ISSCC, the biggest journal for my type of research.

[DonMoose]

Neat!

I just get to deal with the packaged ones.

[vibratoking]

I design ICs. Our back end does the wire bonding, so I don't have to deal with it. I just have to deal with the problems when they don't do it so well.

Good luck with your new chip.

[Cliff Schecht]

It fired up and the currents were about right in the high power linear amplifier side of things. Too bad it oscillated badly and promptly died when I shorted the output to ground with a 10nF cap to try to squash the oscillations. It could have been many things. For now I'm suspecting the lead inductance on the general purpose bonding boards we are using (long dinky leads all running in parallel...AHHH!) combined with the bond wire inductance is enough to make everything go to crap. I thought my gain and phase margins were good but I ran out of time and did not get to do much temperature or process variation sims.

Unfortunately I was a bit too ambitious in my output stage design and made my common source class AB output stage too large. It will try to push out much more current than the MOS can handle because I don't have any current limiting in this first design. Lots of mistakes were made but I've got many more dies to cook and see if I can figure out the issues. It just sucks that my next tapeout in this process is November 1st, not much time at all to get a second revision out!

[Gibsonman63]

Reminds me of having to reserve time on the computer so I could check my Fortran program fed to the computer with a pile of punch cards.

[vibratoking]

Welcome to the IC world.

Not much time to the next tapeout is routine.

Classic mistake of not running full sims because there is no time...only to waste more time after the part arrives because of a problem that was not detected during the full sims that should have been run.

I suppose you are running on an MPW and have no say about the launch date? I have seen MPWs routinely held up because someone needed to run more sims, but that is usually an in-house MPW. What fab and process are you using? For RF designs, we go right to the final MLF package or whatever it is to avoid the long bonds on test chips. Many times the DIL or test bed won't allow for any useful RF testing.

[Zippy]

It fired up and the currents were about right in the high power linear amplifier side of things. Too bad it oscillated badly and promptly died when I shorted the output to ground with a 10nF cap to try to squash the oscillations. It could have been many things. For now I'm suspecting the lead inductance on the general purpose bonding boards we are using (long dinky leads all running in parallel...AHHH!) combined with the bond wire inductance is enough to make everything go to crap.

And you thought you could get away from lead dress issues... Hah!

Best o' luck to getting it sorted out.

[Cliff Schecht]

It works! Sorta!

What I've found is that when configured for unity gain feedback, the op amp oscillates wildly. Since unity gain feedback is the toughest condition in which to achieve stability, this doesn't surprise me so much. At first I tried adding some capacitance to the output (vout to ground) to force stability by reducing the bandwidth but this was ineffective and actually exacerbated the instability problem. I then went back to my sims and found that my design was stable but when I passed off the stuff for layout, the newly created schematic used for layout was not stable. So I configured the op amp on the bench for a gain of 2 and strapped feedback resistor of the op amp (vout to minus) with some capacitance to try band limiting here but still to no avail. The last thing I tried was jacking the gain up to 10 and, under no load, it still oscillated. However when I drop the load resistance down to what the op amp actually will be driving (anywhere from 10 to 20 Ohms from an RF PA collector/drain), everything snapped PERFECTLY into place. With a 7V supply I could achieve up to about 7 MHz of clean swing (6V P-P) and had a 3dB point past 15 MHz (the limit of the HP function gen I am using is 15MHz). I had the linear amp driving 1W into an 8 Ohm load at 3.75 MHz without batting an eye. Attaching the small load resistances drops the gain of the common source AB output stage and helps stability immensely. So while the op amp is obviously under-compensated a bit, it is still usable and might give me some publishable results.

The comparator also worked up to 15 MHz but I could not get it working in its "proper" configuration (which is admittedly tricky). I was able to pipe in external signals and get it to switch as I expected though. I think once I build the entire system and close the loop then this will work as expected as well.

To all of the nay sayers (and there were quite a few) I say FUCK YOU!

While there was a lot I did wrong in this design (all retrospect of course), I at least now have verification that the design process I used is valid and that I can trust the models for the process I'm using, at least up to a certain known extent. I still have a ways to go as far as being an expert but I now know I can shit out an IC in 3 months and not be completely lost. Now I have to do it in a month, my next tapeout is in early November!

If anybody is curious I can post some block diagrams and details on the system that I'm working on. It's essentially a low efficiency linear amplifier in parallel with a high efficiency buck supply. When the op amp poops out, the buck kicks in and provides additional current as needed. The really cool part is that no output capacitance is needed to eliminate the SMPS ripple, the high gain of the op amp (open loop gain of ~80dB) automagically corrects any crap thrown out by the switcher.

[marcoloco961]

Good info Cliff. I'm not quite up to speed enough to understand it all, but I will save this and reference it when I get further. Please post the block diagrams and details on the system that your working on. Very interesting.